Current semiconductor packaging technology often involves tradeoffs between ease and efficiency of manufacturing on the one hand, and various performance drawbacks on the other. For example, lead-frame based packages such as quad flat no-lead (QFN) packages employ lead-frames to facilitate the packaging and singulation of multiple units at once. However, lead-frame based packages, whose connectors are typically placed either on or extending from the sides, tend to have larger footprints than ball grid array (BGA) packages, whose solder ball connectors lie directly underneath the package. Unfortunately, BGA packages have drawbacks as well. Specifically, such packages often employ laminate substrates rather than uniform metal lead-frames, making them more expensive to produce than lead-frame based packages, and less efficiently manufactured.
It is therefore desirable to design packages that employ lead-frames for ease and efficiency of manufacture, but that also have BGA-type solder ball connectors for reduced footprint sizes. In light of the increased requirements for package cost and reliability, it is further desirable to improve various aspects of the design and manufacture of these packages.